setting makefile variables from a shell script

I have a makefile system and it is designed to exec makefiles at each level - each higher level encompassing a greater set of files.  Each makefile can be at any level within the tree.  Each makefile needs to run the Rules.mk file from the top level of the source tree.

My problem is how to make the makefile aware of the top level path. I have a shell script, findtop.sh,  that will do just that. I am now having a problem inserting that into a makefile so that my include of the Rules.mk will work. The findtop script works when run from the command line, but I have had no joy getting it into the makefile. I placed it in the line:
TREE=$(/bin/bash -c findtop.sh)

I tryed placing it before the include with no success.

Can anyone help me find a way to solve this problem????

What would be even more helpful is if the findtop script could actually be placed in the makefile itself. That  will allow me to only have to put one file in each subdir - the makefile itself.

Thanks!
Bill


findtop.sh:
#!/bin/bash

#loop to test if we are in a proper tree
HERE=`pwd`
while [ 1 ]
    do
      cd ..
      CUR=`pwd`
      FIL=`basename $CUR`
      if [ $CUR == "/" ]
      then
      echo Not a Proper Tree!
              exit -1
      fi

      if [ -e "top" ];
      then
              export TREETOP=`pwd`
              cd $HERE
              break
      fi
    done
echo $TREETOP


makefile:
TREE=$(/bin/bash -c findtop.sh)
include $(TREE)/Rules.make

#
# This makefile sets up a dependancy file. This file contains a fully qualified
# list of file names that each source file depends upon.
# If the .depend file does not exist, it will be created.
#
ifeq (.depend,$(wildcard .depend))
all:    targets
include .depend
else
all:    depend targets
endif

# Here we define our target. In this case, the target was defined in
# Rules.make to be a binary file with the same name as sub directory this file
# is in. it is expected to be in the ./bin directory.
targets: $(BINDIR)/$(TARGET)

# This is an alternate method to compile. This will produce individual .o
# files and link them to produce the executable.
$(BINDIR)/$(TARGET): $(OBJS)
      $(CC) -o $(BINDIR)/$(TARGET) $(INCLIST) -L ../lib -lc $(wildcard $(BINDIR)/*.o)

.. etc....
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